Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply

This paper investigates subthreshold voltage operation of digital circuits. Starting from the previously known single supply voltage for minimum energy per cycle, we further lower the energy consumption by using dual subthreshold supplies. Level converters, commonly used in the above threshold design, are found to be unacceptably slow for subthreshold voltage operation. Therefore, special constraints are used to eliminate level converters. We give a new mixed integer linear program (MILP) that automatically and optimally assigns gate voltages, avoids the use of level converters, and holds the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4×4 multiplier we show energy savings of 23% and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. Also, we show energy saving up to 22.2% from the minimum energy point over ISCAS’85 benchmark circuits. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.